High-frequency electronic component and its designing method

专利摘要:
An object of the present invention is to provide a method for easily designing a high frequency electronic component in which a plurality of passive elements are incorporated in a multilayer substrate. A method for designing a high frequency electronic component according to the present invention includes a first step of specifying, for each passive element, a parameter required by each passive element included in a network of a high frequency electronic component to be manufactured, and a parameter of a plurality of passive elements. And a second step of respectively selecting a pattern corresponding to the specified parameter from a database in which a pattern corresponding to the pattern is registered, and a third step of arranging the selected patterns in a transverse direction (horizontal direction) with each other; A fourth step of wiring between patterns is provided.
公开号:KR20040002390A
申请号:KR1020027017530
申请日:2002-04-18
公开日:2004-01-07
发明作者:하야시가츠히코
申请人:티디케이가부시기가이샤；
IPC主号:

专利说明:

High frequency electronic component and its design method {HIGH-FREQUENCY ELECTRONIC COMPONENT AND ITS DESIGNING METHOD}
[2] In recent years, in a communication device represented by a mobile phone or an automobile phone, a high frequency electronic component composed of a multilayer substrate having a plurality of dielectric substrates laminated is used. In such a high frequency electronic component, a plurality of passive elements such as a capacitor (C) and an inductor (L) made of metallization are formed in a multilayer substrate, and they are connected to each other to realize a predetermined function such as a high frequency filter.
[3] Here, a plurality of passive elements formed in a multilayer substrate are formed on different dielectric substrates, whereby a plurality of passive elements are generally three-dimensionally stacked.
[4] However, when a plurality of passive elements formed in a multi-layered substrate are three-dimensionally stacked, electric fields and magnetic fields generated by each passive element easily interact with each other. Therefore, it is essential to design in consideration of such interactions. By the way, since the design which considered such interaction has many parts which depended on the experience of a designer, there existed a problem that the skill of a designer is required.
[5] In addition, after the pattern shape of the metallization is determined by the designer, in general, simulation of the electrical characteristics is performed using an electromagnetic field simulator, which often takes a long time, which prolongs the design of high-frequency electronic components. It was a cause to let.
[1] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency electronic component and a design method thereof, and more particularly, to a high frequency electronic component in which a plurality of passive elements are embedded in a multilayer substrate and a design method thereof.
[39] 1 is a flowchart showing a method for designing a high frequency electronic component according to a preferred embodiment of the present invention;
[40] 2 is an exploded perspective view showing an example of the condenser pattern 10 determined in step S10;
[41] 3 is a schematic cross-sectional view of the condenser pattern 10 shown in FIG.
[42] 4 is an exploded perspective view showing an example of the coil pattern 30 determined in step S10;
[43] 5 is a perspective view plan view of the coil pattern 30 shown in FIG.
[44] FIG. 6 is an exploded perspective view showing an example of the coil pattern 30 'determined in step S10;
[45] 7 is a perspective view plan view of the coil pattern 30 'shown in FIG.
[46] 8 is an example of a network of a high frequency electronic component to be manufactured by the method according to the present embodiment,
[47] 9 is an example in which the passive elements CO to C2 and LO arranged in the low pass filter circuit shown in FIG. 8 are arranged;
[48] Fig. 10 is an exploded perspective view showing the structure of the low pass filter circuit shown in Figs. 8 and 9 in the state where wiring is applied;
[49] 11 is an exploded perspective view showing an example of the condenser pattern 130 determined in step S10;
[50] 12 is a schematic exploded perspective view showing an example of the coil pattern 150 determined in step S10;
[51] FIG. 13 is an exploded perspective view showing the structure of the low-pass filter circuit shown in FIGS. 8 and 9 in a state where wiring is performed;
[52] 14 is an exploded perspective view showing an example in which the electronic component 165 is mounted on the cap layer;
[53] 15 shows an arrangement example of a high frequency electronic component 50 composed of three passive elements 51 to 53;
[54] 16 shows an arrangement example of a high frequency electronic component 60 composed of five passive elements 61 to 65;
[55] 17 shows an arrangement example of a high frequency electronic component 70 consisting of eight passive elements 71 to 78;
[56] FIG. 18 shows an arrangement example of a high frequency electronic component 80 comprising a passive element 81 selected from a series having a side length of 1.0 mm and a passive element 82, 83 selected from a series having a length of 0.5 mm on one side;
[57] Fig. 19 shows an arrangement example of a high frequency electronic component 90 composed of passive elements 91 to 93 selected from a series having a length of 0.5 mm on one side and a passive element 94 selected from a series having a length of 0.3 mm on one side.
[58] FIG. 20 shows an arrangement example of a high frequency electronic component 100 comprising passive elements 101 to 103 selected from a series having a length of 0.5 mm on one side and a passive element 104 selected from a series having a length of 0.8 mm on one side;
[59] 21 is a layout example of a high frequency electronic component 110 composed of six passive elements 111 to 116 of which all planar shapes are rectangular.
[60] 22 shows a passive element 121 (square type) selected from a series of 0.5 mm in length on one side, a passive element 122 (square type) selected from a series of 0.3 mm in length on one side, and a length of 0.5 mm x each side. Example of arrangement of high frequency electronic components 120 comprising passive elements 123 and 124 of 0.3 mm square rectangular type,
[61] 23 is a cross sectional view schematically showing a condenser pattern 170 using five element formation layers;
[62] 24 is a schematic cross-sectional view showing a capacitor pattern 180 using five element formation layers;
[63] 25 is an exploded perspective view showing a high frequency electronic component 190 according to an example in which a ground capacitance is added.
[6] Accordingly, an object of the present invention is to provide a high frequency electronic component in which the interaction between the passive components is reduced in the high frequency electronic component in which a plurality of passive elements are incorporated in the multilayer substrate.
[7] Another object of the present invention is to provide a method for easily designing a high frequency electronic component in which a plurality of passive elements are incorporated in a multilayer substrate.
[8] A method for designing a high frequency electronic component according to the present invention includes a first step of specifying, for each passive element, a parameter required by each passive element included in a network of a high frequency electronic component to be manufactured, and a parameter of a plurality of passive elements. And a second step of respectively selecting a pattern corresponding to each of the specified parameters from a database in which a pattern corresponding thereto is registered, a third step of virtually arranging the selected patterns laterally in the cross direction, and A fourth step of virtually wiring the arranged patterns is provided.
[9] In a preferred embodiment of the present invention, each of the patterns selected in the second step is made of a multi-layer substrate, and the multi-layer substrate is composed of a GND layer provided with a metallization serving as a GND electrode and a main body of a passive element. And a spacer layer provided between the GND layer and the element formation layer.
[10] In a further preferred embodiment of the present invention, in the third step, when the patterns are arranged laterally from each other, the GND layer, the element formation layer and the spacer layer included in each of these patterns constitute the same plane with each other. do.
[11] In more preferable embodiment of this invention, the said 4th step is performed in the said spacer layer contained in at least each said pattern.
[12] In a further preferred embodiment of the present invention, the multilayer substrate further includes a cap layer provided on the side opposite to the spacer layer as viewed from the element formation layer, and a wiring layer provided between the cap layer and the element formation layer.
[13] In more preferable embodiment of this invention, the said 4th step is performed in the said wiring layer contained in at least each said pattern.
[14] In a further preferred embodiment of the present invention, there is further provided a fifth step of mounting the electronic component on the cap layer.
[15] In a further preferred embodiment of the present invention, any of the patterns constituting the capacitor among the patterns selected in the second step includes at least first to third metallization formed in the element formation layer, and the second The metallization of is provided between the said 1st metallization and the said 3rd metallization, The said 1st metallizing is substantially covered by the 2nd metallization the whole of the one surface, The second metallization is substantially covered with its entire surface by the third metallization.
[16] In a more preferable embodiment of the present invention, among the first to third metallizations, the first metallization is closest to the metallization which becomes the GND electrode.
[17] In a further preferred embodiment of the present invention, the pattern constituting the capacitor further comprises a fourth metallization provided between the first metallization and the metallization serving as the GND electrode, and the fourth metallization is performed. The metallization has an area different from that of the first metallization.
[18] In a further preferred embodiment of the present invention, the pattern constituting the coil among the patterns selected in the second step includes the area of the region S1 that is the inner side of the metallized body, which is the main body of the coil, of the element formation layer. And the relationship of the area of the area | region S2 of the outer side is set so that S2≥S1.
[19] In a further preferred embodiment of the present invention, the metallized body of the coil is arcuate.
[20] In a further preferred embodiment of the present invention, the planar shapes of the patterns selected in the second step are the same.
[21] In a further preferred embodiment of the present invention, any planar shape of each pattern selected in the second step is square.
[22] In a further preferred embodiment of the present invention, in the third step, a dummy region is added in the transverse direction with respect to each pattern.
[23] In a further preferred embodiment of the present invention, after the third step is performed, a sixth step of adding an additional layer provided with metallization serving as a capacitor electrode adjacent to the GND layer included in each pattern is provided. It is further provided.
[24] Moreover, the high frequency electronic component which concerns on this invention is a high frequency electronic component which consists of a multilayer board | substrate with a some passive element built-in, The said some passive element is arrange | positioned laterally in the said multilayer substrate, It is characterized by the above-mentioned.
[25] In a preferred embodiment of the present invention, the multi-layered substrate includes a GND layer in which a GND electrode is formed, an element formation layer in which the plurality of passive elements are formed, and a spacer layer provided between the GND layer and the element formation layer, Both input / output terminals of the plurality of passive elements are led out to the spacer layer and are wired in the spacer layer.
[26] In another preferred embodiment of the present invention, the multi-layered substrate includes a GND layer in which a GND electrode is formed, an element formation layer in which the plurality of passive elements are formed, and a wiring layer provided on the side opposite to the GND layer in the element formation layer. All input / output terminals of the plurality of passive elements are led to the wiring layer, and are wired in the wiring layer.
[27] In a more preferred embodiment of the present invention, the plurality of passive elements includes a capacitor, wherein the capacitor includes at least first to third metallization formed on the element formation layer, and the second metal The rise is provided between the first metallization and the third metallization, and the first metallization is substantially covered by the second metallization of the entire surface thereof. The metallization of 2 is substantially covered with the whole of one surface by the said 3rd metallization.
[28] In a further preferred embodiment of the invention, of the first to third metallizations, the first metallization is closest to the GND electrode.
[29] In a further preferred embodiment of the present invention, the capacitor further comprises a fourth metallization provided between the first metallization and the GND electrode, and the fourth metallization is performed by the first metallization. It has a different area than metallization.
[30] In a further preferred embodiment of the present invention, the plurality of passive elements includes a coil, and the coil includes an area of the region S1 inside the metallized metal that is the main body of the coil in the element formation layer, and the coil. The relationship between the area of the area S2 from the metallization serving as the main body to the metallization constituting the end portion of the multilayer substrate or the adjacent passive elements is S2 ≧ S1.
[31] In a more preferred embodiment of the present invention, the metallization constituting the coil is arcuate.
[32] In a further preferred embodiment of the present invention, an electronic component is mounted on the surface of the multilayer substrate.
[33] In a further preferred embodiment of the present invention, the multi-layered substrate further includes an additional layer provided with a capacitive electrode adjacent to the GND layer with the GND electrode as a counter electrode.
[34] Moreover, the high frequency electronic component which concerns on this invention is a high frequency electronic component which consists of a multilayer board | substrate with a some passive element built-in, The said some passive element contains a capacitor | condenser, The said capacitor | condenser is at least 1st-3rd metal A rise, wherein the second metallization is installed between the first metallization and the third metallization, and the first metallization is formed by the second metallization of one surface thereof. The whole is substantially covered, and the second metallization is characterized in that the entirety of one surface thereof is substantially covered by the third metallization.
[35] In a preferred embodiment of the present invention, the multi-layered substrate includes a GND layer having a GND electrode formed almost entirely on its front surface, and among the first to third metallizations, the first metallization is applied to the GND electrode. Closest.
[36] In a further preferred embodiment of the present invention, the capacitor further comprises a fourth metallization provided between the first metallization and the GND electrode, and the fourth metallization is performed by the first metallization. It has a different area than metallization.
[37] Moreover, the high frequency electronic component which concerns on this invention is a high frequency electronic component which consists of a multilayer board | substrate with which several passive elements were built-in, The several passive elements contain the coil, The said coil is the inside of the metallization which becomes a main body. The relationship between the area of the area S1 and the area of the area S2 from the metallization serving as the main body to the metallization constituting the end of the multilayer substrate or the adjacent passive element is characterized by S2 ≧ S1.
[38] In a preferred embodiment of the present invention, the metallized body of the coil is arcuate.
[64] EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail, referring an accompanying drawing.
[65] 1 is a flowchart showing a method for designing a high frequency electronic component according to a preferred embodiment of the present invention.
[66] As shown in Fig. 1, the design method of the high frequency electronic component according to the present embodiment is based on three phases: database creation (phase-1), circuit design (phase-2) and pattern design (phase-3). It is composed. Hereinafter, each phase is explained in full detail.
[67] First, database creation (phase-1) will be described.
[68] Database creation (phase-1) is a phase in which the circuit constants of a plurality of passive elements and structures corresponding thereto are made into a database. First, a virtual structure of a plurality of passive elements is determined by a designer (step S10). .
[69] 2 is an exploded perspective view showing an example of the condenser pattern 10 determined in step S10.
[70] As shown in Fig. 2, the capacitor pattern 10 is constituted by eight dielectric substrates 11 to 18 having a square planar shape and metallization formed on a predetermined dielectric substrate. Among the dielectric substrates 11 to 18, the lowermost dielectric substrate 11 is a GND layer, and a metallization 20 serving as a GND electrode is virtually formed on the entire surface of the dielectric substrate 11. In the dielectric substrates 11 to 18, the dielectric substrates 12 to 14 on the dielectric substrate 11 are spacer layers, and the metallizations 21 and 22 serving as lead-out electrodes of the input and output terminals on the surface of the dielectric substrate 14 are provided. ) Is virtually formed, and no metallization is formed in the other parts. The dielectric substrates 15 to 17 on the dielectric substrate 14 are element forming layers, and the dielectric substrate 15 is virtually formed with a metallization 23 serving as one electrode of the capacitor, and the dielectric substrate 16 is formed. The metallization 24 used as the other electrode of a capacitor | condenser is formed virtually in this, and the metallization 25 used as the one electrode of a capacitor | condenser is virtually formed in the dielectric substrate 17. As shown in FIG. 2, the metallization 23 formed on the dielectric substrate 15 and the metallization 25 formed on the dielectric substrate 17 are virtually formed on the dielectric substrates 16 and 17. The metallization 23 formed on the dielectric substrate 15 and the metallization 21 formed on the dielectric substrate 15 are short-circuited through the through-hole wiring, and the through-hole wiring virtually formed on the dielectric substrate 15. The metallization 24 formed on the dielectric substrate 16 and the metallization 22 formed on the dielectric substrate 14 are short-circuited through the semiconductor substrate 16 to form through hole wirings virtually formed on the dielectric substrates 15 and 16. Shorted through The dielectric substrate 18 on the dielectric substrate 17 is a cap layer, and no metallization is formed.
[71] FIG. 3 is a schematic cross-sectional view of the capacitor pattern 10 shown in FIG. 2.
[72] As shown in FIG. 3, in the capacitor pattern 10, the area of the metallization 23 that is closest to the metallization 20 that becomes the GND electrode is the largest among the metallizations 23 to 25 that become the capacitor electrode. It is small and the area of the metallization 25 farthest from the metallization 20 is set largest. That is, the metallization 24 is substantially covered with the entire surface of the metallization 25, the metallization 23 is substantially covered with the entire surface of the one surface by the metallization 24 have. As a result, the electric field generated at the edges of the capacitor electrodes composed of the metallizations 23 to 25 is directed to the inner side, and leakage of the electric field in the lateral direction (horizontal direction) is effectively reduced. In addition, in this invention, a "lateral direction (horizontal direction)" refers to the direction which extends the main surface of each dielectric substrate which comprises a high frequency electronic component, ie, the direction orthogonal to the lamination direction of a dielectric substrate. For this reason, with such a structure, even if another circuit element is arrange | positioned with respect to the said capacitor | condenser electrode in the horizontal direction (horizontal direction), interaction between them becomes very small.
[73] Moreover, when the metallizing 23-25 which comprises a capacitor | condenser electrode is made into such a structure, even if a shift | deviation arises in metallization 23-25 in an actual product, the fluctuation of the capacitance value resulting from this is suppressed. You might get the effect. In addition, since the capacitance between the metallization 20 serving as the GND electrode and the metallizations 23 to 25 can be made substantially uniform, the impedances of the two input / output terminals 21 and 22 can be made substantially the same. have.
[74] 4 is an exploded perspective view showing an example of the coil pattern 30 determined in step S10.
[75] As shown in FIG. 4, the coil pattern 30 has a square plane shape similar to the condenser pattern 10, and the length of one side of the eight dielectric substrates 31 to 38, which is the same as the condenser pattern 10, and It is comprised by the metallization formed on the predetermined dielectric substrate. Among the dielectric substrates 31 to 38, the lowermost dielectric substrate 31 is a GND layer, and a metallization 40 serving as a GND electrode is virtually formed on the upper surface thereof. In the dielectric substrates 31 to 38, the dielectric substrates 32 to 34 on the dielectric substrate 31 are spacer layers, and the metallizations 41 and 42 serving as lead-out electrodes of the input / output terminals on the surface of the dielectric substrate 34 are shown. ) Is virtually formed, and no metallization is formed in the other parts. The dielectric substrates 35 to 37 on the dielectric substrate 34 are element forming layers, and metallizations 43 to 45 are virtually formed on the dielectric substrates 35 to 37, respectively.
[76] 4, one end 43a of the metallization 43 formed on the dielectric substrate 35 and the metallization 41 formed on the dielectric substrate 34 are attached to the dielectric substrate 35. The other end 43b of the metallization 43 formed on the dielectric substrate 35 and the one end 44a of the metallization 44 formed on the dielectric substrate 36 are short-circuited through the virtually formed through-hole wiring. And the other end 44b of the metallization 44 formed on the dielectric substrate 36 and the metallization 45 formed on the dielectric substrate 37, short-circuited through the through hole wirings virtually formed on the dielectric substrate 36. One end 45a of the () is short-circuited through the through-hole wiring virtually formed in the dielectric substrate 37, and the other end 45b and the dielectric substrate 34 of the metallization 45 formed on the dielectric substrate 37. The metallization 42 formed thereon is formed through the through hole wirings virtually formed in the dielectric substrates 35 to 37. It is shorted. The dielectric substrate 38 on the dielectric substrate 37 is a cap layer, and no metallization is formed.
[77] FIG. 5 is a schematic perspective plan view of the coil pattern 30 shown in FIG. 4.
[78] As shown in FIG. 5, in the coil pattern 30, the area of the area | region S1 enclosed by the metallization 43-45 which comprises a coil, and the area | region S2 of the outer side (end of a dielectric substrate) Relationship) is set such that S2 S1. As a result, most of the magnetic field generated in the region S1 passes through the region S2, so that leakage of the magnetic field in the lateral direction (horizontal direction) is effectively reduced. In other words, if S1> S2, the magnetic flux density of the magnetic field becomes maximum in S1, and thus, in S2, a magnetic field having a higher magnetic flux density cannot be made. For this reason, much more magnetic field will leak outward than S2.
[79] Therefore, by setting S2 to S1, even if other circuit elements are arranged in the lateral direction (horizontal direction) with respect to the coil pattern 30, the interaction between them becomes very small.
[80] In addition, in the coil pattern 30 shown in FIG. 4 and FIG. 5, although the area | region enclosed by the metallization 43-45 is made into a rectangle, you may make it circular.
[81] FIG. 6 shows the metallization 43 'to 45' on the dielectric substrates 35 to 37 as an arc shape, whereby the area enclosed by the metallization 43 'to 45' is circular (circular). An exploded perspective view showing a coil pattern 30 'according to one example, and FIG. 7 is a schematic perspective plan view of the coil pattern 30' shown in FIG.
[82] Also in the coil pattern 30 ', the area of the area S1 surrounded by the metallizations 43' to 45 'constituting the coil, and the area of the area S2 (up to the end of the dielectric substrate) outside the coils 30a. The relationship is set so that S2 S1, whereby the same effect as that of the coil pattern 30 described above can be obtained. In addition, in the coil pattern 30 ', since the metallization 43'-45' is circular arc shape, even if another circuit element is arrange | positioned in the horizontal direction (horizontal direction) with respect to the said coil pattern 30 ', The ends of the metallizations 43 'to 45' are not parallel to the ends of the metallization constituting the other circuit element, and therefore, the magnetic coupling with the other circuit element is weakened. . Moreover, in the coil pattern 30 ', since the metallization 43'-45' is circular arc shape, a high frequency electric current does not concentrate locally, for this reason, the effect which the Q value of a coil improves is also acquired.
[83] As mentioned above, in step S10, the structure of the predetermined passive element which consists of one GND layer, three spacer layers, three element formation layers, and one cap layer is determined.
[84] When the structure of the passive element is determined in step S10, this structure is then input to the electromagnetic simulator, and the electromagnetic field simulation by the electromagnetic simulator is performed (step S11). In the electromagnetic simulation, it is calculated which circuit constant the passive element having the structure input by the designer has. Specifically, the S parameter of the input / output terminal in the predetermined frequency band is calculated. In such an electromagnetic field simulation, the electromagnetic field distribution of the metallization pattern formed on the dielectric material follows the equation of the mark cell, which is calculated using a finite element method or the like. In the passive element to be simulated, since the pattern structure has a three-dimensional arrangement as shown in FIGS. 2 to 7, it is preferable to use a three-dimensional electromagnetic field simulator.
[85] In addition, unlike the electromagnetic simulation of the whole circuit performed in the conventional design method of the high frequency electronic component, the electromagnetic simulation performed in this step S11 is performed with respect to a single passive element. It doesn't take much time like simulation.
[86] As a result, a circuit constant (parameter) of the passive element and a structure (pattern) corresponding thereto can be obtained. By doing this for a plurality of passive elements, a database can be created (step S12).
[87] In this case, also in the case of registering the capacitor pattern which has a characteristic different from the capacitor pattern 10 in a database, like the capacitor pattern 10, it becomes a GND electrode among the metallization 23-25 used as a capacitor electrode. It is preferable to set the area of the metallization 23 closest to the metallization 20 to be the smallest, and to set the area of the metallization 25 farthest to the metallization 20 to be the largest. Thereby, all the capacitor | condensers registered in the database can be set as the capacitor | condenser by which the leakage of the electric field to the horizontal direction (horizontal direction) was reduced effectively. However, it is not necessary to make the electrode structure as mentioned above with respect to the capacitor | condenser with a small leak sufficiently in the horizontal direction (horizontal direction) of an electric field, even if it is not made as the electrode structure mentioned above.
[88] Similarly, in the case where a coil pattern having a different characteristic from the coil pattern 30 is registered in the database, it is preferable to set S2 ≥ S1 as in the coil pattern 30. Thereby, all the coils registered in the database can be made into the coil which the leakage of the magnetic field to the horizontal direction (horizontal direction) reduced effectively.
[89] As described above, each passive element registered in the database can be a passive element with little interaction in the lateral direction (horizontal direction).
[90] Next, the circuit design (phase-2) will be described.
[91] The circuit design phase-2 is a phase for determining a circuit element configuration (network) of a high frequency electronic component to be manufactured. First, a network of the high frequency electronic component to be manufactured is input to a network simulator, and the input network is required. The circuit constant (S parameter) of each passive element constituting the network is calculated so as to have the electrical characteristics to be obtained (step S20). That is, the network simulator calculates electrical characteristics by substituting an integer into each circuit element constituting the input network, and uses an optimization function called an optimizer so that the electrical characteristics of the input network have required electrical characteristics. The integer value required for each circuit element constituting the network is found.
[92] 8 is an example of a network of high-frequency electronic components to be produced by the method according to the present embodiment.
[93] The circuit shown in FIG. 8 is a low pass filter circuit, and is comprised by three capacitor | condenser CO-C2 and one coil LO. Therefore, when the network of the high frequency electronic component to be manufactured has such a structure, the element constant value required for each of capacitor | condenser CO-C2 and coil LO is discovered.
[94] In this way, the S parameter in the circuit is calculated for the constant value of each passive element constituting the network. This S parameter is referred to a database created in database creation (phase-1), and among the registered passive elements, passive elements having S parameters calculated in step S20 are selected, and these are substituted into the network. (Step S21). In this case, when the passive element having the S parameter of the circuit element calculated in step S20 is not registered in the database, among the passive elements registered in the database, an S parameter close to the parameter calculated in step S20. It is good to select two passive elements having a and to create the parameter and the corresponding pattern by using a complementary method or the like, or to return to database creation (phase-1) and register a new one.
[95] Next, the network simulator again calculates the electrical characteristics of the entire network, which has been substituted, and judges whether or not it satisfies the specifications required for the high frequency electronic component to be manufactured (step S22).
[96] As a result, if it is determined that the specification is not satisfied, the process returns to step S21 where another passive element is selected from the passive elements registered in the database, and substitution into the network is performed again. On the other hand, when it is determined that the specification is satisfied, the circuit design (phase-2) is terminated, and then the process moves to the pattern design (phase-3).
[97] Next, the pattern design phase-3 will be described.
[98] The pattern design phase-3 is actually a phase for starting high-frequency electronic components, and first of all, from the passive elements registered in the database created in database creation phase-1, the circuit design phase-2 is used. Each passive element whose usage has been determined is selected, and the pattern is virtually arranged in the horizontal direction (horizontal direction) (step S30).
[99] FIG. 9 shows an example in which the passive elements CO to C2 and LO which form the low pass filter circuit shown in FIG. 8 are arranged.
[100] As shown in Fig. 9, in step S30, it is important that each passive element to be used is arranged in the transverse direction (horizontal direction). In this case, as described above, since the planar shape of each passive element registered in the database is square, various combinations can be taken as the arrangement of the passive elements CO to C2 and LO. In addition, each of the passive elements registered in the database has the same layer structure including one GND layer, three spacer layers, three element formation layers, and one cap layer. As shown in Fig. 9, when the passive elements are arranged in the transverse direction (horizontal direction), the GND layer, the spacer layer, the element formation layer, and the cap layer constituting each of the passive elements are all located on the same plane.
[101] When the virtual arrangement of the passive elements is completed in this manner, the virtual wiring between these passive elements is performed next (step S31).
[102] FIG. 10 is an exploded perspective view showing the structure of the low-pass filter circuit shown in FIGS. 8 and 9 in the state where wiring is performed.
[103] As shown in Fig. 10, wiring between each passive element is performed using a spacer layer, and no wiring is performed on the element formation layer. As a result, wiring between the passive elements can be performed without substantially considering variations in the parameters of the passive elements. As a result, the structure of the entire high-frequency electronic component to be produced is determined.
[104] When the structure of the whole high frequency electronic component to be manufactured is determined, a mask is actually produced based on this (step S32), and a high frequency electronic component is actually started using this mask (step S33).
[105] In the high-frequency electronic component started as described above, since passive elements having small interactions in the transverse direction (horizontal direction) are arranged in the transverse direction (horizontal direction) with each other, there is very little interaction between the passive elements. For this reason, as described above, the passive elements registered in the database are virtually arranged (step S30) and wired by using the spacer layer (step S31), so that the structure of the entire high-frequency electronic component to be produced is obtained. It is possible to obtain, and there is no need to consider the interaction between each passive element.
[106] Therefore, according to the design method of the high frequency electronic component which concerns on this embodiment, since design can be performed without resorting to the designer's experience, it becomes possible to design without being an expert designer. In addition, since it is not necessary to perform the electromagnetic field simulation of the whole high frequency electronic component, it becomes possible to design a high frequency electronic component in a shorter time.
[107] Moreover, although the case where a low pass filter was designed was demonstrated as the example in the said embodiment, even when manufacturing various high frequency components other than this, since the database created in database creation (phase-1) can be used, As the number of passive elements increases, the design of various high frequency electronic components can be performed more easily and in a short time.
[108] Next, another preferred embodiment of the present invention will be described.
[109] The design method of the high frequency electronic component according to the present embodiment is basically the same as that of the design method of the high frequency electronic component according to the embodiment (see FIG. 1), but the design of the passive element in the database preparation (phase-1) ( In the step S10) and the passive element wiring (step S31) in the pattern design phase-3, it differs from the design method of the high frequency electronic component by the said embodiment. In other words, in this embodiment, the structure of the passive elements to be registered in the database and the wiring method between the passive elements are different from the above embodiment.
[110] FIG. 11: is an exploded perspective view which shows an example of the capacitor | condenser pattern 130 determined in step S10 in this embodiment.
[111] As shown in Fig. 11, the capacitor pattern 130 is constituted by nine dielectric substrates 131 to 139 having a square planar shape and metallization formed on a predetermined dielectric substrate. Among the dielectric substrates 131 to 139, the lowermost dielectric substrate 131 is a GND layer, and a metallization 140 serving as a GND electrode is virtually formed on its entire surface. In the dielectric substrates 131 to 139, the dielectric substrates 132 and 133 on the dielectric substrate 131 are spacer layers, and no metallization is formed. In addition, the dielectric substrates 134 to 136 on the dielectric substrate 133 are element formation layers, and a metallization 141 serving as one electrode of the capacitor is virtually formed on the dielectric substrate 134, and the dielectric substrate 135 is formed. The metallization 142 which becomes the other electrode of the capacitor | condenser is virtually formed in this, and the metallization 143 which becomes one electrode of the capacitor | condenser is virtually formed in the dielectric substrate 136. As shown in FIG. The dielectric substrates 137 and 138 on the dielectric substrate 136 are wiring layers, and metallizations 144 and 145 serving as lead electrodes of the input / output terminals are virtually formed on the surface of the dielectric substrate 137.
[112] Here, as shown in FIG. 11, the metallization 141 formed on the dielectric substrate 134 and the metallization 143 formed on the dielectric substrate 136 are through holes formed virtually in the dielectric substrates 135 and 136. The metallization 143 formed on the dielectric substrate 136 and the metallization 144 formed on the dielectric substrate 137 are short-circuited through the wiring, and through the through-hole wiring virtually formed in the dielectric substrate 137. The metallization 142 formed on the dielectric substrate 135 and the metallization 145 formed on the dielectric substrate 137 are short-circuited through the through hole wirings virtually formed on the dielectric substrates 136 and 137. . The dielectric substrate 139 on the dielectric substrate 138 is a cap layer, and no metallization is formed.
[113] Also in the condenser pattern 130 shown in FIG. 11, among the metallizations 141 to 143 serving as the capacitor electrodes, the area of the metallization 141 nearest to the metallization 140 serving as the GND electrode is the smallest. The area of the metallization 143 furthest from the rise 140 is set largest. That is, the metallization 142 is substantially covered with the entire surface of the metallization 143, and the metallization 141 is substantially covered with the entire surface of the metallization 142. have. As a result, in the condenser pattern 130, similarly to the condenser pattern 10 described above, the electric field generated at the edge of the condenser electrode is directed inward, and leakage of the electric field in the lateral direction (horizontal direction) is effectively reduced. At the same time, even when a deviation occurs in the metallizations 141 to 143 in the actual product, fluctuations in capacity values due to this are suppressed. In addition, since the capacitance between the metallization 140 serving as the GND electrode and the metallizations 141 to 143 can be made substantially uniform, the impedances of the two input / output terminals 144 and 145 can be made substantially the same.
[114] 12 is a schematic exploded perspective view showing an example of the coil pattern 150 determined in step S10 in the present embodiment.
[115] As shown in FIG. 12, the coil pattern 150, like the capacitor pattern 130, has a planar square shape and a length of one side of the dielectric substrates 151 to 159 that is the same as the capacitor pattern 130. And metallization formed on a predetermined dielectric substrate. Among the dielectric substrates 151 to 159, the lowermost dielectric substrate 151 is a GND layer, and a metallization 160 serving as a GND electrode is virtually formed on its entire surface. In the dielectric substrates 151 to 159, the dielectric substrates 152 and 153 on the dielectric substrate 151 are spacer layers, and no metallization is formed. Dielectric substrates 154 to 156 on the dielectric substrate 153 are element formation layers, and metallizations 161 to 163 are formed on the dielectric substrates 154 to 156, respectively. In addition, the dielectric substrates 157 and 158 on the dielectric substrate 156 are wiring layers, and metallization 164 and 165 serving as the extraction electrodes of the input / output terminals are virtually formed on the surface of the dielectric substrate 157.
[116] 12, one end 161a of the metallization 161 formed on the dielectric substrate 154 and one end 162a of the metallization 162 formed on the dielectric substrate 155 may be a dielectric material. The other end 162b of the metallization 162 formed on the dielectric substrate 155 and the metallization 163 formed on the dielectric substrate 156 are short-circuited through a through hole wiring virtually formed in the substrate 155. One end 163a is short-circuited through the through-hole wiring virtually formed in the dielectric substrate 156, and is formed on the other end 163b and the dielectric substrate 157 of the metallization 163 formed on the dielectric substrate 156. The formed metallization 164 is short-circuited through the through-hole wiring virtually formed in the dielectric substrate 157, and the other end 161b and the dielectric substrate 157 of the metallization 161 formed on the dielectric substrate 154. The metallization 165 formed on the surface is virtually formed on the dielectric substrates 155 to 157. Short-circuited through the through-hole wiring. The dielectric substrate 159 on the dielectric substrate 158 is a cap layer, and no metallization is formed.
[117] Also in the coil pattern 150 shown in FIG. 12, the area of the area S1 surrounded by the metallizations 161 to 163 constituting the coil, and the area S2 (up to the end of the dielectric substrate) on the outer side thereof. The relationship between the areas is set so that S2≥S1. Thereby, also in the coil pattern 150, the leakage of the magnetic field to the horizontal direction (horizontal direction) is effectively reduced similarly to the coil pattern 30 mentioned above.
[118] In addition, in the coil pattern 150 shown in FIG. 12, the area S1 surrounded by the metallizations 161 to 163 constituting the coil has a rectangular shape. The coil pattern 150 shown in FIGS. 30 '), the shape of the metallization which comprises a coil may be made into circular arc shape, and the area | region S1 may be made circular by this. The effect by making the shape of the metallizing 161-163 which comprises a coil into arc shape is as above-mentioned.
[119] As mentioned above, in this embodiment, in step S10, the predetermined passive element which consists of one GND layer, two spacer layers, three element formation layers, two wiring layers, and one cap layer is carried out. The structure of is determined.
[120] As for the passive element having such a structure, an electromagnetic field simulation (step S11) is performed similarly to the above embodiment, whereby the circuit constants (parameters) and the structure (pattern) corresponding to the various passive elements are obtained. ) Is created (step S12).
[121] The circuit design Phase-2 is similar to the above embodiment, and the circuit element configuration (network) of the high frequency electronic component to be produced is determined by the above-described method. When the circuit design (phase-2) is finished, the pattern design (phase-3) is continued. In the present embodiment, first, among the passive elements registered in the database created in the database creation (phase-1), In the circuit design (phase-2), each passive element whose use has been determined is selected, and the pattern is virtually arranged in the horizontal direction (horizontal direction) (step S30).
[122] For example, when the passive elements CO to C2 and LO that constitute the low pass filter circuit shown in FIG. 8 are disposed, as shown in FIG. 9, the passive elements used are transverse to each other. It is arranged in the (horizontal direction). In addition, in this embodiment, any passive constitution of each passive element registered in the database has one layer of GND layer, two layers of spacer layer, three layers of element formation layer, two layers of wiring layer, and one layer of Since it has the same layer structure consisting of a cap layer, as shown in FIG. 9, when each passive element is arranged in the transverse direction (horizontal direction), the GND layer, spacer layer, element formation layer, wiring layer, All the cap layers are located on the same plane.
[123] When the virtual arrangement of the passive elements is completed in this manner, the virtual wiring between these passive elements is performed next (step S31).
[124] FIG. 13 is an exploded perspective view showing the structure of the low-pass filter circuit shown in FIGS. 8 and 9 in the state where wiring is performed.
[125] As shown in Fig. 13, in the present embodiment, the wiring between each passive element is performed using the wiring layer, and the GND wiring is constituted by through-hole wiring provided in the spacer layer, and the wiring is not performed in the element formation layer. . Thereby, wiring between each passive element can be performed, without considering the variation of the parameter of each passive element substantially. As a result, the structure of the entire high-frequency electronic component to be produced is determined.
[126] When the structure of the whole high frequency electronic component to be manufactured is determined, a mask is actually produced based on this (step S32), and a high frequency electronic component is actually started using this mask (step S33).
[127] In the high-frequency electronic components started by the method according to the present embodiment, since any passive elements with small interaction in the lateral direction (horizontal direction) are arranged in the lateral direction (horizontal direction) with each other, the interaction between each passive element Is very small, and the same effect as the above embodiment can be obtained.
[128] In addition, in this embodiment, since wiring between each passive element is performed using the wiring layer located between a cap layer and an element formation layer, as shown in FIG. 14, a PIN diode is formed on the surface (cap layer) of a high frequency electronic component. In the case of mounting an active component such as an active component or an electronic component 165 such as a capacitor, a coil, or a resistor as a discrete component, it is easy to wire the electronic component 165 with a passive element formed in the element formation layer. It becomes possible. In addition, when the electronic component 165 is mounted on the surface (cap layer) of the high frequency electronic component, the pad electrode 166 for such a component is required on the surface (cap layer) of the high frequency electronic component. Since the wiring layer is interposed between the cap layer and the element formation layer, the influence of the pad electrode 166 on the passive element formed in the element formation layer can be reduced.
[129] In the capacitor pattern 130 shown in FIG. 11, metallizations 141 to 143 serving as capacitor electrodes are formed on all three dielectric substrates 134 to 136 serving as element formation layers. In the small capacitor pattern, it is not necessary to use all of the three dielectric substrates 134 to 136 which are the element formation layers, and metalization may be formed only on the two dielectric substrates 135 and 136 on the upper layer side. Similarly, in the coil pattern 150 shown in FIG. 12, metallizations 161 to 163 serving as coil electrodes are formed on all three dielectric substrates 154 to 156 serving as element formation layers. In the small coil pattern, it is not necessary to use all of the three dielectric substrates 154 to 156 which are the element formation layers, and only the uppermost dielectric substrate 156 or the upper two dielectric substrates 155 and 156 are used. Only metallization should be formed. In this case, in this embodiment, since the wiring layer is provided above the element formation layer, and the metallization 144, 145, 164, 165 which becomes an electrode of one side and the other of a capacitor | condenser or a coil is formed here, it is necessary to draw out these electrodes. The number of through holes made can be reduced.
[130] In the low pass filter circuit shown in Fig. 13, a GND wiring made of a through hole is provided in the spacer layer. However, when the GND wiring is unnecessary in the circuit configuration, it is not necessary to provide such a through hole in the spacer layer. .
[131] In each of the embodiments described above, an example of designing a low pass filter composed of four passive elements has been described. However, when the total number of passive elements cannot be used to form a quadrilateral shape, You can do it together.
[132] FIG. 15 shows an arrangement example of a high frequency electronic component 50 composed of three passive elements 51 to 53.
[133] As shown in FIG. 15, when the high frequency electronic component consists of three passive elements 51 to 53, by adding the dummy region 54, the planar shape of the entire high frequency electronic component 50 can be quadrilateral. have. Here, the dummy region 54 has a structure in which the metal layer is not formed on the other dielectric substrate, except that the GND electrode is provided on the lowermost dielectric substrate.
[134] Fig. 16 shows an arrangement example of the high frequency electronic component 60 composed of five passive elements 61 to 65. Figs.
[135] As shown in FIG. 16, when the high frequency electronic component consists of five passive elements 61-65, the dummy area 66 is added, and the planar shape of the whole high frequency electronic component 60 can be quadrilateral. have.
[136] Moreover, even if it can arrange | position entirely quadrangular by the number of passive elements used, you may add a dummy area.
[137] 17 shows an arrangement example of the high frequency electronic component 70 composed of eight passive elements 71 to 78.
[138] Since the high frequency electronic component 70 is composed of eight passive elements 71 to 78, the entire high frequency electronic component 70 can be arranged in a quadrilateral shape without adding a dummy region. As shown in FIG. 17, the dummy region 79 is disposed. By adding, the planar shape of the whole high frequency electronic component 70 can be made into the shape which is easier to handle. In this case, since the dummy region 79 is disposed at the center of the high frequency electronic component 70, the effect that the interaction between the passive elements is further reduced is also obtained.
[139] In each of the above embodiments, the case in which the lengths of one side of the passive elements registered in the database are equal to each other has been described as an example. However, the lengths of one side of the passive elements do not have to be all the same, for example, Manuals belonging to the appropriate series are registered according to the electrical characteristics required for the high frequency electronic components to be produced by registering a plurality of series having different lengths of one side such as side lengths of 1.0 mm, 0.8 mm, 0.5 mm, and 0,3 mm. You may use an element. In this case, it is not necessary to select only one series of passive elements to be used with respect to one high frequency electronic component, but may select high frequency electronic components by selecting from two or more series and arranging them.
[140] Fig. 18 shows an arrangement example of a high frequency electronic component 80 composed of a passive element 81 selected from a series having a side length of 1.0 mm and a passive element 82,83 selected from a series having a side length of 0.5 mm. .
[141] As shown in Fig. 18, even when a passive element is selected from two or more series, it is possible to make the planar shape of the entire high-frequency electronic component into quadrilateral.
[142] When the passive element is selected from two or more series and cannot be arranged in a quadrangular shape as a whole, the planar shape of the entire high-frequency electronic component can be quadrilateral by adding a dummy region.
[143] Fig. 19 shows an arrangement example of a high frequency electronic component 90 composed of passive elements 91 to 93 selected from a series of 0.5 mm in length on one side, and passive elements 94 selected from a series of 0.3 mm in length on one side.
[144] As shown in Fig. 19, when the passive element 94 whose length of one side is smaller than the other passive elements 91 to 93 is used, and it cannot be arranged in a quadrangular shape as a whole, the dummy region 95 is added to provide a high frequency. The planar shape of the entire electronic component 90 can be quadrilateral. In this case, as shown in FIG. 19, by arranging the passive element 94 having a side length of 0.3 mm at the corner portion and the remaining portion as the dummy region 95, the interaction between each passive element is further reduced. can do.
[145] Fig. 20 shows an arrangement example of the high frequency electronic component 100 comprising passive elements 101 to 103 selected from a series of 0.5 mm in length on one side, and passive elements 100 selected from a series of 0.8 mm in length on one side.
[146] As shown in Fig. 20, when the passive element 104 having one side length larger than the other passive elements 101 to 103 is used, and it cannot be arranged in a quadrangular shape as a whole, the dummy regions 105 and 106 are added to provide high frequency. The planar shape of the entire electronic component 100 can be quadrilateral.
[147] In each of the above embodiments, the case where any of the passive elements registered in the database are square is described as an example, but the planar shapes of all the passive elements do not need to be square, and the planar shape is rectangular. Passive devices may be registered in the database.
[148] FIG. 21 shows an arrangement example of a high frequency electronic component 110 made up of six passive elements 111 to 116 that are all rectangular in planar shape.
[149] As shown in Fig. 21, even when the passive elements 111 to 116 used are rectangular, by arranging them in the lateral direction (horizontal direction), the planar shape of the entire high frequency electronic component 110 can be quadrilateral. . In this case, when it is not possible to arrange the quadrilateral as a whole by the number of passive elements used, as shown in Figs. 15 and 16, by adding a dummy region, the planar shape of the entire high-frequency electronic component can be quadrilateral. have. Moreover, even if it can arrange | position entirely quadrangular by the number of passive elements used, you may add a dummy area as shown in FIG.
[150] In addition, in the case of using a passive element having a rectangular planar shape, it is not essential to select all passive elements constituting the high frequency electronic component from the type of which the planar shape is rectangular, and with respect to one high frequency electronic part, the planar shape is square. A passive element may be selected from both the type and the type whose plane shape is rectangular, and the high frequency electronic components may be configured by arranging them. In this case, in order to make the planar shape of the whole high-frequency electronic component into a quadrangle, the length of each side of a passive element having a planar shape is equal to the length of one side of a passive element having a square shape, or an integer multiple or an integer distribution thereof. It is preferable to set it to 1. For example, if a passive element of a square shape is a passive element, and a plurality of series each having a length of 1.0 mm, 0.8 mm, 0.5 mm, or 0.3 mm is registered in the database, the planar shape is a rectangular type. As the passive element of, the length of each side is equal to the length of one side of the passive element of the square type, or the length of each side, such as 0.8 mm x 0.5 mm or 1.0 mm x 0.5 mm. It is preferable to make the length of at least one side equal to an integer multiple or one times the length of one side of the passive element of the square-type type, such as 0.4 mm x 0.5 mm or 0.4 mm x 0.6 mm.
[151] Fig. 22 shows a passive element 121 (square type) selected from a series of 0.5 mm in length on one side, a passive element 122 (square type) selected from the Q series of 0.3 mm in length on one side, and a length of 0.5 mm in each side. The arrangement example of the high frequency electronic component 120 which consists of passive elements 123 and 124 of rectangular type which is x 0.3 mm.
[152] As shown in Fig. 22, the length of each side of a passive element having a rectangular planar shape, even when a square type passive element 121, 122 and a rectangular type passive element 123, 124 are mixed as a passive element to be used. If the planar shape is equal to the length of one side of a passive element having a square shape or is set to an integer multiple or an integer multiple thereof, the planar shape of the entire high frequency electronic component 120 can be quadrilateral. In this case, when the total number of passive elements used and the size of the passive elements cannot be arranged in a quadrilateral shape, the planar shape of the entire high-frequency electronic component can be quadrilateral by adding a dummy region. Moreover, even if it can arrange | position in quadrilateral as a whole by the number and size of passive elements used, you may add a dummy area.
[153] The present invention is not limited to the above embodiments, and various changes are possible within the scope of the invention described in the claims, and it goes without saying that they are also included within the scope of the present invention.
[154] For example, in the above embodiment, in the creation of the database (phase-1), the characteristics (parameters) of each passive element are determined by the determination of the virtual structure of the passive element (step S10) and the electromagnetic field simulation (step S11). And a structure (pattern) corresponding to this, but the passive element is actually started and the electrical characteristics thereof are measured to obtain the characteristics (parameters) of the passive element and the corresponding structure (pattern). In this case, while more accurate data on the characteristics (parameters) of the passive elements and the structures (patterns) corresponding to them can be obtained, a large amount of time is required to generate one data. For this reason, as in the above embodiment, it is most preferable to compensate for this by generating data by the determination of the virtual structure (step S10) and the electromagnetic field simulation (step S11), and starting and measuring as necessary.
[155] In addition, in the above embodiment, an example of designing a low pass filter has been described. As the high frequency electronic component which can be designed according to the present invention, it is not limited to the low pass filter, and other circuits such as filters, couplers, It is also possible to design a PIN switch. In this case, if necessary, a semiconductor element such as a PIN diode or an electronic component such as a capacitor, a coil, or a resistor as a discrete component may be mounted on the surface (cap layer) of the high frequency electronic component. In addition, as in the former embodiment, in the case where these electronic components are mounted on the surface of the high frequency electronic component in which no wiring layer is provided between the surface (cap layer) of the high frequency electronic component and the element formation layer, a passive element embedded in the multilayer board. It is preferable to form a wiring for connecting the electronic component with the dummy region. If such wiring is formed in the dummy region, there is an advantage that it is not necessary to change the metallization pattern in the element formation layer of each passive element.
[156] In the capacitor patterns 10 and 130 described above, metallizations 23 to 26, 141 to 143 serving as capacitor electrodes are formed over three layers, and in the coil patterns 30 and 150 described above, all of them are Metallizations 43 to 46 and 161 to 163 serving as coil electrodes are formed over three layers. When a larger integer value is required, four or more layers may be assigned as the element formation layer. In this case, it is preferable to set the area of each metallization used as a capacitor electrode as follows.
[157] 23 is a schematic cross-sectional view showing a capacitor pattern 170 using five element formation layers.
[158] As shown in FIG. 23, in the capacitor pattern 170, the metallization 175 is formed from the metallization 175 that is furthest from the metallization 176 that becomes the GND electrode among the metallizations 171 to 175 serving as the capacitor electrode. In order of the metallization 171 closest to 176, it sets so that area may become small. In other words, the metallization 175 serving as the uppermost layer has the largest area, and the other metallizations 171 to 174 are substantially covered with the entire surface of each one by the adjacent upper metallization. As a result, the same effects as those of the capacitor patterns 10 and 130 described above can be obtained.
[159] 24 is a schematic cross-sectional view showing a capacitor pattern 180 using five element formation layers.
[160] As shown in FIG. 24, in the capacitor pattern 180, the area of the metallization 185 farthest from the metallization 186 serving as the GND electrode is the metallization 181 to 185 serving as the capacitor electrode. It is set larger than the metallization 184 immediately below, the area of the metallization 184 is set larger than the metallization 183 immediately under it, and the area of the metallization 183 is the metallization immediately below it ( It is set smaller than 182, and the area of the metallization 182 is set larger than the metallization 181 just under it. That is, among the plurality of metallizations serving as the capacitor electrodes, three metallizations located far from the metallization serving as the GND electrodes are similar to the metallization serving as the GND electrodes as in the capacitor patterns 10 and 130 described above. The area of the metallization which is set so as to be small and which has a different area from the metallization which is adjacent to the metallization which becomes the GND electrode with respect to the other metallization among the plurality of metallizations which become the capacitor electrode is obtained. The area is set smaller than.
[161] Also in such a structure, the electric field generated at the edges of the capacitor electrodes composed of the metallizations 181 to 185 is directed inward, and leakage of the electric field in the lateral direction (horizontal direction) is effectively reduced. In addition, according to such a structure, it becomes possible to obtain a capacitance value larger than that of the capacitor pattern 170 shown in FIG.
[162] In addition, in the coil pattern 30 mentioned above, the area of the area | region S1 enclosed by the metallization 43-45 which comprises a coil, and the area of the area | region S2 (up to the edge part of a dielectric substrate) of the outer side. The relationship is set to be S2 S1, but even in S1> S2, the dummy region to be added in the placement step of the passive element (step S30) or the blank region in the adjacent passive element (metallization in the element formation layer). Can be arranged so that S2 S1 as a result, it is also possible to register such a coil pattern in a database and use it. That is, the region S2 at the time when the virtual arrangement of the passive elements (step S30) is completed may be defined by the region from the metallization constituting the coil to the metallization in the end portion of the dielectric substrate or the adjacent passive element. Can be.
[163] Moreover, in the coil pattern 30 'mentioned above, although the coil shape which consists of metalization 43'-45' is an inverted shape, you may make an elliptical coil shape according to the planar shape of a dielectric substrate.
[164] In each of the above embodiments, after the virtual arrangement of the passive elements (step S30) is performed in the pattern design Phase-3, the wiring between these arranged passive elements is performed (step S31) and step S30. )), The ground capacitance may be added to the lower layer than the GND layer by adding a dielectric substrate on which the ground capacitance electrode is formed and another GND layer.
[165] 25 is an exploded perspective view showing the high frequency electronic component 190 according to the example in which such a ground capacitance is added.
[166] As shown in FIG. 25, in the high frequency electronic component 190, first and second additional layers are provided below the GND layer, which is originally the lowest layer. The first additional layer is formed by forming a metallization 192 serving as a ground capacitance electrode on the dielectric substrate 191, and the second additional layer is a GND electrode almost on the entire surface of the dielectric substrate 193. The metallization 194 is formed. In addition, a cutout 196 is provided in the metallization 195 originally provided on the GND layer, which is the lowest layer, and the metallization 192 serving as the ground capacitance electrode is formed through the through hole provided in the cutout 196. It is connected to the wiring formed in the spacer layer.
[167] According to the high frequency electronic component 190 which has such a structure, the earth capacitance with a comparatively large capacity can be formed easily. In this case, since the first and second additional layers are provided below the GND layer, there is little influence on the passive element provided in the element formation layer.
[168] Incidentally, in each of the above embodiments, the number of stacked dielectric substrates constituting the passive element is one example, and the number of stacked high frequency electronic components according to the present invention is not limited to that shown in the above embodiments. Therefore, for example, four or more dielectric substrates may be used as the element formation layer, or four or more dielectric substrates may be used as the spacer layer. Moreover, also regarding a wiring layer, it is not limited to two layers, Only one layer may be sufficient and three or more layers may be sufficient.
[169] In the latter embodiment, the wiring between the passive elements is performed in the wiring layer provided between the cap layer and the element formation layer. The wiring between each passive element may be performed in both of the wiring layer and the spacer layer.
[170] As described above, according to the present invention, it is possible to provide a high frequency electronic component in which the interaction between the passive elements is reduced. Further, according to the present invention, it is possible to easily design a high frequency electronic component in which a plurality of passive elements are incorporated in a multilayer substrate.

权利要求:
Claims (31)
[1" claim-type="Currently amended] From the first step of specifying the parameters required for each passive element included in the circuitry of the high frequency electronic component to be manufactured for each passive element, the database of the parameters of the plurality of passive elements and the pattern corresponding thereto, A second step of respectively selecting a pattern corresponding to each of the specified parameters, a third step of virtually arranging the selected pattern in a transverse direction to each other, and a fourth step of virtually wiring between the arranged patterns A method of designing a high frequency electronic component, comprising the steps.
[2" claim-type="Currently amended] The metallization according to claim 1, wherein each of the patterns selected in the second step is made of a multi-layered substrate, and the multi-layered substrate is a metalized body formed of a main body of a passive element and a GND layer provided with metallization serving as a GND electrode. And a spacer layer provided between the GND layer and the element formation layer.
[3" claim-type="Currently amended] The pattern forming apparatus according to claim 2, wherein in the third step, when the patterns are arranged in the transverse direction, the GND layer, the element formation layer, and the spacer layer included in each of the patterns constitute the same plane. Method of designing high frequency electronic components.
[4" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 2, wherein the fourth step is performed at least in the spacer layer included in each of the patterns.
[5" claim-type="Currently amended] 3. The high frequency electronic component of claim 2, wherein the multilayer substrate further comprises a cap layer disposed on the side opposite to the spacer layer as viewed from the element formation layer, and a wiring layer provided between the cap layer and the element formation layer. Design method.
[6" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 5, wherein the fourth step is performed at least in the wiring layer included in each of the patterns.
[7" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 5, further comprising a fifth step of mounting the electronic component on the cap layer.
[8" claim-type="Currently amended] The pattern of claim 2, wherein any of the patterns constituting the capacitor among the patterns selected in the second step include at least first to third metallizations formed in the element formation layer, and the second metallization is The first metallization is provided between the first metallization and the third metallization, and the first metallization is substantially covered by the second metallization, and the entire surface thereof is substantially covered by the second metallization. Metallization is a method for designing a high frequency electronic component, characterized in that the entire surface of the one surface is substantially covered by the third metallization.
[9" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 8, wherein, among the first to third metallizations, the first metallization is closest to the metallization which is the GND electrode.
[10" claim-type="Currently amended] 10. The method of claim 9, wherein the pattern constituting the capacitor further comprises a fourth metallization provided between the first metallization and the metallization which is the GND electrode, wherein the fourth metallization is A method of designing a high frequency electronic component, characterized by having an area different from the first metallization.
[11" claim-type="Currently amended] The area | region of the area | region S1 used as the inner side of the metallization which becomes a main body of a coil among the said element formation layers, and the outer side of the pattern of Claim 2 selected from the said 2nd step. A method for designing a high frequency electronic component, characterized in that the relationship between the areas of the areas S2 is set so that S2
[12" claim-type="Currently amended] 12. The method for designing a high frequency electronic component according to claim 11, wherein the metallization that forms the main body of the coil is an arc.
[13" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 1, wherein the planar shape of each pattern selected in the second step is the same.
[14" claim-type="Currently amended] The method of designing a high frequency electronic component as claimed in claim 1, wherein all of the planar shapes of the patterns selected in the second step are square.
[15" claim-type="Currently amended] The method of designing a high frequency electronic component according to claim 1, wherein in the third step, a dummy region is added in the transverse direction with respect to each pattern.
[16" claim-type="Currently amended] The method according to claim 2, further comprising, after the third step is performed, a sixth step of adding an additional layer provided with metallization serving as a capacitor electrode adjacent to the GND layer included in each pattern. A high frequency electronic component design method characterized by the above-mentioned.
[17" claim-type="Currently amended] A high frequency electronic component comprising a multi-layer substrate having a plurality of passive elements embedded therein, wherein the plurality of passive elements are arranged laterally in the multi-layer substrate.
[18" claim-type="Currently amended] 18. The plurality of substrates of claim 17, wherein the multilayer substrate comprises a GND layer having a GND electrode formed thereon, an element formation layer having the plurality of passive elements formed thereon, and a spacer layer provided between the GND layer and the element formation layer. Both the input and output terminals of the passive element are drawn to the spacer layer and are wired in the spacer layer.
[19" claim-type="Currently amended] 18. The semiconductor device according to claim 17, wherein the multi-layered substrate includes a GND layer having a GND electrode formed thereon, an element formation layer having the plurality of passive elements formed thereon, and a wiring layer provided on the opposite side of the GND layer as viewed from the element formation layer. A high-frequency electronic component, characterized in that both input and output terminals of a passive element are drawn out to the wiring layer and wired in the wiring layer.
[20" claim-type="Currently amended] 19. The device of claim 18, wherein the plurality of passive devices include a capacitor, wherein the capacitor includes at least first to third metallizations formed on the device formation layer, and the second metallization is the first metallization. The first metallization is provided between the first metallization and the third metallization, and the first metallization is substantially covered by the second metallization in its entirety, and the second metallization Is a high frequency electronic component, wherein the entire surface thereof is substantially covered by the third metallization.
[21" claim-type="Currently amended] 21. The high frequency electronic component of claim 20, wherein the first metallization is closest to the GND electrode among the first to third metallizations.
[22" claim-type="Currently amended] 22. The method of claim 21, wherein the capacitor further comprises a fourth metallization provided between the first metallization and the GND electrode, wherein the fourth metallization is different from the first metallization. A high frequency electronic component having a different area.
[23" claim-type="Currently amended] 23. The area of the area S1 of any one of claims 18 to 22, wherein a plurality of passive elements includes a coil, and the coil is an inner side of the metallized part of the element formation layer that is the main body of the coil. And the area of the area (S2) from the metallization serving as the main body of the coil to the metallization constituting the end portion of the multilayer board or the adjacent passive element is S2≥S1.
[24" claim-type="Currently amended] 24. The high frequency electronic component as claimed in claim 23, wherein the metallization constituting said coil is arcuate.
[25" claim-type="Currently amended] 18. The high frequency electronic component as set forth in claim 17, wherein an electronic component is mounted on a surface of the multilayer board.
[26" claim-type="Currently amended] 19. The high frequency electronic component of claim 18, wherein the multilayer substrate further comprises an additional layer provided with a capacitor electrode adjacent to the GND layer, the capacitor electrode having the GND electrode as a counter electrode.
[27" claim-type="Currently amended] A high frequency electronic component comprising a multilayer substrate having a plurality of passive elements embedded therein, wherein the plurality of passive elements include a capacitor, the capacitor including at least first to third metallizations, and the second metallization. Is disposed between the first metallization and the third metallization, and the first metallization is substantially covered with the entire surface of one of the first metallizations by the second metallization. The metallization of the high frequency electronic component, characterized in that the entire surface of the surface is substantially covered by the third metallization.
[28" claim-type="Currently amended] 28. The method of claim 27, wherein the multi-layered substrate includes a GND layer having a GND electrode almost formed on its entire surface, and wherein the first metallization is closest to the GND electrode among the first to third metallizations. High frequency electronic components.
[29" claim-type="Currently amended] 29. The method of claim 28, wherein the capacitor further comprises a fourth metallization provided between the first metallization and the GND electrode, wherein the fourth metallization is different from the first metallization. A high frequency electronic component having a different area.
[30" claim-type="Currently amended] A high frequency electronic component comprising a multi-layer substrate having a plurality of passive elements embedded therein, wherein the plurality of passive elements include coils, and the coils have an area of the inner region S1 of the metallized structure as the main body and the main body. A relationship between the area of the area S2 from the metallization to the metallization constituting the end of the multilayer board or the adjacent passive elements is S2≥S1.
[31" claim-type="Currently amended] 31. The high frequency electronic component as claimed in claim 30, wherein the metallization of the main body of the coil is arcuate.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US10110191B2|2018-10-23|High-frequency laminated component and laminated high-frequency filter

---

JP4336497B2|2009-09-30|High frequency printed circuit board vias

---

US7442092B2|2008-10-28|Electrical connector with improved crosstalk compensation

---

JP4376493B2|2009-12-02|Printed circuit board

---

KR100640130B1|2006-10-31|Integrated circuit interconnect system

---

KR101298288B1|2013-08-20|Method and inductor layout for reduced vco coupling

---

US7092236B2|2006-08-15|Multilayer chip capacitor

---

KR100541089B1|2006-01-11|Laminated low pass filter

---

US6137376A|2000-10-24|Printed BALUN circuits

---

US8355258B2|2013-01-15|Support method and apparatus for printed circuit board

---

US7339452B2|2008-03-04|Embedded inductor and application thereof

---

US7136274B2|2006-11-14|Embedded multilayer printed circuit

---

CA2622456C|2015-01-27|Systems and methods for electromagnetic noise suppression using hybrid electromagnetic bandgap structures

---

US8680950B2|2014-03-25|Multilayer bandpass filter

---

TW512654B|2002-12-01|Highly integrated multi-layer circuit module having multi-layer ceramic substrates and embedded passive devices

---

US7423500B2|2008-09-09|Low-pass filter capable of preventing unnecessary electromagnetic coupling

---

US7884697B2|2011-02-08|Tunable embedded inductor devices

---

US7927153B2|2011-04-19|Communications connector with multi-stage compensation

---

US5055816A|1991-10-08|Method for fabricating an electronic device

---

KR100428900B1|2004-04-29|Laminated impedance device

---

JP4525864B2|2010-08-18|Laminated balance filter

---

KR100534169B1|2005-12-06|Multi-laminated inductor and manufacturing method thereof

---

JP2015043439A|2015-03-05|Common mode choke coil and high frequency electronic device

---

JP2016524816A|2016-08-18|Vector inductor with multiple interconnected metallization layers resulting in high quality factor

---

US5382925A|1995-01-17|Hybrid coupler

同族专利:

---

公开号 | 公开日

---

US20040207487A1|2004-10-21|

---

TW561368B|2003-11-11|

---

JP2003016133A|2003-01-17|

---

WO2002089021A1|2002-11-07|

---

EP1394702A1|2004-03-03|

---

KR100466677B1|2005-01-15|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
2001-04-27|Priority to JP2001132605

---

2001-04-27|Priority to JPJP-P-2001-00132605

---

2001-05-30|Priority to JP2001162904A

---

2001-05-30|Priority to JPJP-P-2001-00162904

---

2002-04-18|Application filed by 티디케이가부시기가이샤

---

2004-01-07|Publication of KR20040002390A

---

2005-01-15|Application granted

---

2005-01-15|Publication of KR100466677B1

优先权:

---

申请号 | 申请日 | 专利标题

---

JP2001132605|2001-04-27|

---

JPJP-P-2001-00132605|2001-04-27|

---

JP2001162904A|JP2003016133A|2001-04-27|2001-05-30|High-frequency electronic component and its designing method|

---

JPJP-P-2001-00162904|2001-05-30|